A Power Reduction technique for Flash analog-to-digital converter

The primary objective of this book is to showcase a new high performance comparator for low-power application of Flash ADC. Moreover by employing the proposed comparator the designed Flash ADCs get rid of power hungry reference-ladder network. The secondary objective is to propose a novel power reduction technique for high-speed Flash ADC which examines the inactive comparators in the Flash ADC and disables them to save the unnecessary power consumption.