Analysis of Low Power Methodologies for Multiplier

This research work has found an innovative method of designing as adder which is efficient in operating with low power smaller area and lower PDP. The proposed design was implemented in a Ripple Carry Adder (RCA) to compare the performance with other methods described in this dissertation. As the contribution of this work is primarily focused on low power and the hierarchical approach gives knowledge about design strategies the literature on hierarchical approaches for power optimization were given as literature review. 1 bit full adders like BBL-PT ULPFA TGA TFA SERF and regular CMOS methods were discussed as past adders along with recent designs by researchers. Though there are various design techniques existing with unique advantages the circuit level approach has been taken in this research due to the scope for construction of a full custom design. The proposed MOSSI-ULP adder is constructed with the integration of PMOS and NMOS transistors as switches than the familiar logic families. This helps to reduce the application of supply voltage and hence power reduction is possible to obtain Multiplier which consume Low Power.