Analysis of SRAM Cells for Power Reduction Using Low Power Techniques

The design total power static power dynamic power Transient time transient delay and static current in 8T SRAM and 10T SRAM cell are calculated and compared. The 8T SRAM has the least transistor count and least area efficient but speed of operation is somewhat reduced. Further increase in the transistor count in 10T SRAM cell however makes area and delay large in room temperature. When temperature increases from a particular value the 10T SRAM cell performs better than the 8T SRAM cell. This justifies the use of 10T SRAM cell for low power applications with varying temperature conditions. The proposed SRAM memory design can be implemented in any digital circuit.