Architecture of a Activation Function Layer Employing Composite Charge Reuse Methodology for Tech-Enabled Settings

<p>Very Large Scale Integration (VLSI) involved in the Integrated Circuit (IC) formation by merging millions of Metal Oxide Semiconductor (MOS) transistors in a single chip. These ICs are preferred in most of the security applications due to its physical and electrical properties. In this modern digital world security plays an important role to protect the personal information from the hackers. Since security is one of the emerging fields various kind of security issues are analyzed and different kinds of security approaches are presented by the researchers to mitigate these issues. The researchers not only focused the security they also focused an optimized design. The design should occupy less area low power consumption and it should achieve high performance. However in the VLSI field considerations like area power and latency are traded off. The design of digital circuits is a challenging and tedious task because it consumes more power due to the utilization of functional integration blocks clock speed geometrical process etc. The scaling process employed in the design enhanced the number of transistors as well as operation of the chip. But the scaling process can attain high speed leads to high performance of the overall design. The voltage scaling process reduced the threshold voltage but gradually increased the leakage current.</p>