Design and Implementation of Area-Efficient Dual-Mode Double Precision

Floating point division is a core arithmetic widely used in scientific and engineering applications. This work proposed architecture for double precision floating point division. This architecture is designed for dual-mode functionality which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation. For this a novel dual mode Radix-4 Modified Booth multiplier is designed which is used iteratively in the architecture of dual-mode mantissa computation. Other key components of floating point division flow (such as leading-one-detection left/right dynamic shifters rounding etc.) are also re-designed for the dual-mode operation. The proposed dual- mode architecture is synthesized using UMC 90nm technology ASIC implementation. Two versions of proposed architecture are presented one with single stage multiplier and another with two stage multiplier. Compared to a standalone double precision division architecture the proposed dual-mode architecture requires 17% to 19% extra hardware resources with 3% to 5% period overhead.