Design and Implementation of Floating Point Vedic Multiplier in VHDL

Multiplication is important operation in most of the signal processing applications.Hencemultiplier is the crucial part of signal processing applications like FIR filterIIR filterFFTDFTDCT etc.Sothere is always need of a multiplier which is high speedwhich consumes less area and low power.Hence performance of multiplier has direct effect on the final applications in which multipliers are used. In this book we have tried to design optimized Vedic multiplier in HDL which can give good delay and area performance.As FIRIIR filter have their coefficient in fractionwe have designed the multiplier in single precision floating point format. Henceaccuracy and range of multiplication coefficient is more. The Vedic multiplier is further used in FIR filerIIR filter and Haar Wavelet transform as a basic building block.Alsoit is compared with FIR filterIIR filter and Haar Wavelet transform using other multipliers such as Shift and Add multiplierArray multiplierand Wallace multiplier based on delay and area performance.