Design and Optimisation of Carry Select Adder

Among various arithmetic operations addition is the most commonly used operation and is being performed by adder. Therefore adder delay defines the maximum frequency of operation of the chip.Demand for high-speed adders is always increasing since present microprocessors use high clock frequencies and low voltage power supplies. This book offers a comprehensive treatment of adders with focus on optimization of Carry Select Adder. It focuses on maximizing the performance by minimizing the Power Dissipation and Delay. This book also includes the synthesis and simulation of adders in VHDL. It also reviews the fundamental concepts of VHDL. Analytical study of Carry Select Adder has been done using the method of Logical Effort.