DESIGN HIGH SPEED AND HIGH ACCURACY NOVEL MULTIPLIER

This book summarizes the In this project work Design and Implementation Of High Speed and high Accuracy Novel Multiplier using PPA is implemented. Approximate circuits are becoming an effective solution to accurately operating circuits if energy efficiency is concerned and the application is error tolerant. One of the primary features that help us determine the computational power of a processor is the speed of its arithmetic unit. PPA adder architecture therefore greatly enhances the speed of the overall process. This proposed system has less delay and requires less area and its efficiency is compared with some of previous approximate and accurate multipliers in terms of power area and delay. The corresponding architecture based on the proposed algorithm is then synthesized by Xilinx ISE and it is observed that the proposed structure has lower area-delay complexity than the best of existing designs.