Design & implementation of digital components using Rev. Logic Gates

Implementing the already existing circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS quantum computing nanotechnology optical computing etc. Reversible logic gates offer significant advantages such as high speed low power ease of fabrication …etc. Also circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis is to minimize the garbage to minimize the delay to minimize the total number of gates and also to minimize the width of the circuit. In this paper designer implemented 2:1 MUX D-Flip-Flop Vedic multiplier and PIPO shift register using reversible logic gates.