Design of Cost-Efficient Interconnect Processing Units

<p><strong>Streamlined Design Solutions Specifically for NoC</strong><br>To solve critical network-on-chip (NoC) architecture and design problems related to structure performance and modularity engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.</p><p><strong>A Balanced Analysis of NoC Architecture</strong><br>As the first detailed description of the commercial Spidergon STNoC architecture <strong>Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC</strong> examines the highly regarded cost-cutting technology that is set to replace well-known shared bus architectures such as STBus for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced well-organized structure simple teaching methods numerous illustrations and easy-to-understand examples the authors explain:</p><ul> <p> </p> <li>how the SoC and NoC technology works</li> <li>why developers designed it the way they did</li> <li>the system-level design methodology and tools used to configure the Spidergon STNoC architecture</li> <li>differences in cost structure between NoCs and system-level networks</li> </ul><p>From professionals in computer sciences electrical engineering and other related fields to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics such as technological deep sub-micron effects homogeneous and heterogeneous processor architectures multicore SoC interconnect processing units generic NoC components and embeddings of common communication patterns. </p>