Design of Low Leakage SRAM

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been the relatively minor area. However in the current VLSI process the sub-threshold current becomes one of the major factors of the power consumption especially in high-end memory. To reduce the leakage power in the SRAM the power gating method can be applied and a major technique of the power gating is using sleep transistors to control the sub-threshold current. In this project dual threshold voltages are adopted; normal SRAM cells have lower threshold voltages and the higher threshold voltages control the sleep transistors. The size of sleep transistors can be chosen by the worst case current and are applied to every block.