Design of Low Power High Speed Level Shifters For Multi VDD Systems

The power consumption and speed performance of VLSI circuits can be optimised by number methodologies the methodologies which involve power supply voltage reduction is consider as effective and efficient technique as decreases in power supply voltage leads to reduction of speed performance and power consumption of the VLSI design. The best approach called as Clustered Voltage Scaling means sectoring the entire design into different voltage blocks or islands and all high-speed sensitive blocks are operated with core voltage VDDH to attain the speed performance and low-speed sensitive blocks or islands can be operated with lower supply voltage VDDL to reduce the power consumption. The key interfacing circuits in multi supply designs are the voltage Level Shifters (LSs). The voltage LSs acts as voltage translators between VDDL and VDDH voltage blocks or voltage islands. This book address about Development of high performance LSs they are capable of voltage shifting from low voltage to high voltage and vice versa based on its input voltage with lower power consumption and delay.