DIGITAL DESIGN THROUGH VERILOG

Book Contain of Introduction to Verilog HDL: Verilog as HDL Levels of Design Description Concurrency Simulation and Synthesis Programming Language Interface Module. Language Constructs and Conventions: Introduction Keywords Identifiers White Space Characters Comments Numbers Strings Logic Values Data Types Scalars and Vectors Operators. Gate Level Modeling: Introduction AND Gate Primitive Module Structure Other Gate Primitives Illustrative Examples Tristate Gates Array of Instances of Primitives Design of Flip-Flops with Gate Primitives Gate Delay Strengths and Contention  Resolution Net Types.