Digital Design Through Verilog

The book contains: Introduction to Verilog HDL: Verilog as HDL Levels of Design Description Concurrency Simulation and Synthesis Programming Language Interface Module. Language Constructs and Conventions: Introduction Keywords Identifiers White Space Characters Comments Numbers Strings Logic Values Data Types Scalars and Vectors Operators. Gate Level Modeling: Introduction And Gate Primitive Module Structure Other Gate Primitives Illustrative Examples Tristate Gates Array of Instances of Primitives Design of Flip-Flops with Gate Primitives Gate Delay Strengths and Contention Resolution Net Types. Modeling at Data-flow Level: Introduction Continuous Assignment Structure Delays and Continuous Assignments Assignment to Vector Operators. Behavioral Modeling: Introduction Operations and Assignments ''Initial'' Construct Always construct Assignments with Delays ''Wait Construct'' Design at Behavioral Level Blocking and Non-blocking Assignments The ''Case'' Statement ''If'' and ''if-Else'' Constructs ''Assign-De-Assign'' Constructs ''Repeat'' Construct for loop ''The Disable'' Construct ''While Loop'' Forever Loop sequential and Parallel Blocks.