Enhanced Low power CMOS Current Mirror Design

With the advent of the portable electronic and mobile communication systems low-voltage and low-power mixed mode circuit design has gained importance. For the operation of such systems like hearing aids implantable cardiac pacemakers cell-phones and hand held multimedia terminals etc. battery is the main source of power. They require low power dissipation so as to have reasonable battery life and weight. Designing High Performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. Level shifted low voltage CMOS current mirror topology was selected and optimized to get the desired results by varying dimensions of transistors and biasing voltages. Dynamic range has improved by a factor of 800µA and bandwidth has improved by more than 189 MHz as compared to the reference work. The power dissipation has improved by more than 40%.