Hardware Architectures for Post-Quantum Digital Signature Schemes

<p>This book explores C-based design implementation and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification.  The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective especially focusing on C-based design power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.<br></p><p></p><p></p><p></p><p></p><p></p><p></p><ul><li>Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based code-based and multivariate-based;</li><li>Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;</li><li>Enables designers to build hardware implementations that are resilient to a variety of side-channels.</li></ul>