Hybrid 4-bit full-adder circuits based on the novel full-swing gates

This book summarizes the XOR XNOR and C signals are only used so no additional NOT gates need to generate the C signal whereas if the C signal is also used to produce the Sum output then XOR and XNOR signals will not drive the Sum output through the TG multiplexer but only they will be connected to the data select lines of 2-1-MUX. So the capacitance of XOR and XNOR nodes becomes smaller and the delay of the circuit will be improved. In the future D‐flip flop based on XOR/XNOR circuits can be designed more efficiently. As technology is getting advanced power consumption delay time and chip area are the main concern issues that we have to improve therefore these circuits can be designed to solve these issues more efficiently to reduce the total cost of the system by optimizing transistors’ sizes.