Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits

Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied grade: 6 Anna University course: PhD language: English abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes Linear-decompression-based schemes and Broadcast-scan-based schemes.The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.