IC Design of CMOS UHF RFID Analog Front End

The application of ultra high frequency (UHF) radio frequency identification (RFID) has been gaining momentum since the ratification of EPC Class 1 Gen 2 (EPC C1G2 also known as ISO 18000-6C) protocol. The limited availability of Schottky barrier diode (SBD) has stimulated the investigation of alternate circuit solutions to fabricate UHF RFID chips of comparable performance using typical CMOS processes. UHF RFID analog front end has four building blocks: UHF RF-to-DC rectifier voltage reference and regulator modulator and demodulator. This book identified Dynamic Threshold MOSFET (DTMOST) as a promising device under ultra low power application and explored circuit topologies and design methodologies employing DTMOST for the UHF RFID AFE. All circuit designs and analyses were based on a CMOS 0.18µm Single Polysilicon Six Metal Layers (1P6M) triple well technology. Performance gain power consumption area penalty and design considerations associated with the DTMOST techniques were compared and contrasted against the traditional cells.