LOW POWER ADDER DESIGN for VLSI

This wok proposes an energy efficient approximate adder that provides low power high performance addition without severe quality degradation. The proposed adder introduces area efficient approximate logic that is used to adder least significant bits of the adder. The effectiveness of the adder is analyzed over the well known accurate and approximate adders by implementing on Tanner and MATLAB. The simulation result shows that proposed adder outperform over the existing adder and can be effectively applied to the applications that can tolerate small amount of error.