Method to address CMOS design performance decline due to PVT variation

Since the onset of the new millennium power consumption related complications such as heat dissipation battery lifetime and reliability have resulted in drastic shifts in silicon industry priorities so that performance is no longer the only pivotal motivation in the design of integrated circuits. Instead energy consumption restrictions are transforming the design methods and smart sensor applications are simultaneously exacerbating this trend by pressing for extremely long if not indefinite battery lifetime. However this shift and proliferation in the semiconductor industry has come at a substantial price which is a growing inaccuracy in the fabrication process of integrated circuits with each technology generation. When operating in ultra-low power situations the impact of this inaccuracy affects the circuits to a greater extent makes them vulnerable to voltage and temperature variations and can simply render them inoperable. This study proposes a novel technique that is highly sensitive to fabrication process variations while monitoring and appropriately responding to temperature and voltage variations.