Modeling and Simulation of Gate Mislaignment Effect in MOSFETs

Rupendra Kumar Sharma received Ph.D. degree in electronics from the University of Delhi India in 2010. His Ph.D thesis was on the modeling simulation and characterization of gate misalignment effect in DG MOSFETs. Dr. Sharma was a Postdoctoral Researcher with the Department of Electronics (DEIS) University of Bologna Italy where he was involved in numerical optimization and characterization of a dual N/P channel super-junction LDMOS for low dropout voltage regulator (LDO) applications. He has also served as a Marie-Curie experienced researcher for the Telecommunication Systems Institute; Technical University of Crete Greece on a European Funding Research Program Compact Modeling Network (COMON) on compact modeling of nanoscale multi-gate MOSFETs and of high-voltage MOSFETs. Currently He is working on the project Silicon carbide based power devices and their applications for power savings funded by European Social Fund in collaboration with Czech Science Foundation at the Faculty of Electrical Engineering Czech Technical University in Prague. He has authored or coauthored over 32 papers in various international journals and conference proceedings.