Nano-Transistor Scaling and their Characteristics using Monte Carlo

Chapter 1 gives detail of numerical results for 25nm SiNANO scale MOSFETs ((Metal Oxide Semiconductor Field Effect Transistor) using self-consistent ensemble Monte Carlo (MC) device simulation. The simulated results are electron velocity sheet density drain current with the shortening of gate length in the channel area and ID - VG characteristics. Chapter 2 gives an overview on scaling of Si and In0.3Ga0.7As MOSFETs from a gate length of 25 nm to gate lengths of 20 15 10 and ultimately 5 nm is carried out using ensemble Monte Carlo (MC) device simulations with quantum corrections. Chapter 3 includes a description of Electron mobility as a function of ionised impurity concentration is calculated in bulk GaAs using ensemble Monte Carlo simulations. The simulations include Fermi-Dirac statistics with self-consistently calculated Fermi energy and electron temperature. Chapter 4 gives an explanation on investigation about the effect of electron confinement in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1- D Poisson - Schrödinger equation.