Optimal Interconnect Networks for 2D and 3D Microchips

We are today in the era of gigascale 2D and 3D integrated circuits. These microchips are typically considered to be interconnect limited with performance limited by signal power clock and thermal interconnect networks. Techniques to tackle this interconnect challenge are proposed and quantitatively evaluated in this book. Topics described by the author include integrated microchannel cooling of 3D stacked dice repeater insertion models carbon nanotube interconnects parallel processing architectures electromigration avoidance methods and a CAD tool to co-design signal power clock and thermal interconnect networks of microchips. This book should be especially useful to students and professionals in the areas of microelectronics VLSI design packaging and computer architecture.