Optimal Size of Reorder Buffer to Implement ILP in Superscalar

Instruction-level parallelism is the key factor to improve CPU performance. ILP can be achieved in superscalar processor at micro-architecture level with the help of various components like reservation station reorder buffer branch predication etc. This book is effort to find a best possible size of reorder buffer to achieve significant level of ILP. This book elaborates the process to find optimal size of reorder buffer using PSATsim simulator. In this book Mr. Mathur had elaborated effect of various reservation station structure and various benchmarks types on reorder buffer. Based on the data analysis of these metrics Mr. Mathur tries to finally evaluate the most favorable size of reorder buffer.