Optimized Hardware Realization of Computationally Intensive Algorithms

Computationally Intensive algorithms such as those used in image and signal processing multimedia telecommunications cryptography networking and computation in general were first realized using software running on programmable Digital Signal Processors (DSPs) or microprocessors. However with advancements in Very Large Scale Integration (VLSI) technology hardware realization has become an attractive alternative. Significant speedup in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the inherent parallelism in the algorithms. Recent advancements in Field Programmable Gate Array (FPGA) technology and availability of advanced Electronic Design Automation (EDA) tools have made it possible to efficiently realize computation intensive algorithms using low cost hardware. In this monograph two distinct algorithms one from image processing and other from DSP domain are optimally realized in FPGA.