Performance Analysis of InP Based Hemt Devices in Nano Regime

In silicon CMOS technology scaling inhibits the device performance to a wide extent due to increased power dissipation and short channel effects. Therefore the need for alternative material and technology has become predominant for future devices in the nanometer regime. As the device scaling continues to the sub 20 nm regime III-V compound semiconductors based High Electron Mobility Transistors (HEMTs) have become promising candidates replacing Si-based devices for future VLSI applications. Also these III-V compound HEMT have dominated the market with superior performance in terms of high reliability compared to other devices such as silicon nanowires and carbon nanotubes. III-V materials such as InGaAs InAlAs and InAs based HEMTs are favorable devices for THz range frequency applications. The choice of a proper channel material (InGaAs sub-channel / InAs composite channel) and optimization of channel thickness (TCH) Barrier thickness(TB) and a gate length (Lg) in HEMT structure create low crystal related lattice defects improved mobility high DC and analog / RF performances.