Performance Analysis of Ternary Multiplier using Booth Encoding

In the world of VLSI the abundance of battery powered handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area the power consumption and the device speed. The high speed data processing low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation delay and area has been done effectively.