Prevention of SoC Failure with Cache Write Management Techniques

Advent of Very Large Scale Integration (VLSI) technology enables embedding of a large class of electronic circuits within a chip. As per Moore's law transistor counts are getting doubled every two years. Chip multiprocessors (CMPs) therefore integrates thousands of on-chip cores and multi-layer on-chip cache to support the memory demand of those cores that accredits complex multi-programmed environment. But the large sized cache consumes huge percentage of total power and occupies an appreciable chip floor area. On-chip nonvolatile memory (NVM) is advantageous as compared to SRAM or DRAM. However NVM more specifically Resistive memories suffer from write endurance issue under workload variation and Malicious attacks. Variable cell lifetime is also observed in such memories. Multiple cells of ReRAM encounters stuck-at faults. Cellular automata (CA) technology is considered almost everywhere in physical and biological systems as powerful models. CA is applied in pattern recognition networking cryptography VLSI testing computer architecture etc. The objective is to introduce design of a robust ReRAM based memory subsystem for CMPs with cache write management techniques.