Reconfigurable Platform to Design an Adaptive Filter to Denoise ECG

Improvements in capacity performance and decrease in cost FPGAs have become a viable solution for making custom chips and programmable DSP devices. Baseline wander noise removal from Electrocardiogram (ECG) signal is very complex problem. In ECG signal baseline wander noise distorts the low frequency segments. Heart attack related information is retrained from ST segment so it is very necessary to have a noise free ECG signal. This Research work presents Design and implementation of an architecture for a LMS based Adaptive filter to minimize Baseline wander noise Power line noise and high frequency EMG noise from (ECG) signal. This architecture is implemented on FPGA using Spartan 3s400pq208-4 board and Xilinx system Generator (XSG) software. The signals under experiment are retrieved from MIT-BIH database and are added with Different noises. Efficient removal of Baseline wander noise Power line noise and high frequency EMG noise is verified and observations are noted for getting desirable SNR. This research work is carried out by using FPGA for adaptive filter using LMS Algorithm to remove Baseline wander noise Power line noise and high frequency EMG noise.