SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE

Increasing the complexity of the electronic systemsleads to electronic system level modeling conceptsupporting hardware and software co-design andco-verification environment in a single framework.SystemC an IEEE approved electronic designstandard for system design and verificationprocesses provides such an environment by supportinga wide range of abstraction levels from system-levelto register-transfer level. In this book twodifferent models of a processor core whoseinstruction set architecture is compatible withTI MSP430 microcontroller are designed byemploying the classical hardware modeling capabilityof the SystemC. With its well-designed orthogonalinstruction set elegant addressing modes usefulconstant generators and flexible von-Neumannarchitecture 16-bit RISC-like processor of theMSP430 microcontroller is an ideal selection for theSoC designs. Instruction set and addressing modes ofthe designed processors are simulated thoroughly.Moreover original CRC programs are used to verifythe processor cores. SystemC tohardware flow is also illustrated by synthesizing theALU part of the processor into a Xilinx-based hardware.