Visualization Concept for FPGA Internal States

The book provides an insight to the development process of a simple yet flexible and expandable Intellectual Property core. The run-time configurable IP helps the end user to view the user selected internal statistics and parameters in real time overlayed on an existing video stream. The readers will get to know in detail the modular architecture of the IP with block diagrams state diagrams and simulation models. After reading the book the they will be aware of the different stages of an IP development along with the different protocols standards timing issues & constraints and other critical concepts like Clock Domain Crossings (CDC) used in FPGA development. This would be sufficient for them to built their own custom IPs without requiring any external help. The readers who are new to Field Programmable Gate Arrays (FPGAs) or are not programmers would get a platform to begin with and the readers who have already started their FPGA journeys would find answers to the questions they have been looking for or will be looking for in the near future.